By R. Joobbani
Routing of VLSI chips is a crucial, time eating, and hard challenge. the trouble of the matter is attributed to the big variety of usually conflicting elements that have an effect on the routing caliber. conventional suggestions have approached routing by way of ignoring a few of these components and implementing pointless constraints with a view to make routing tractable. as well as the imposition of those regulations, which simplify the issues to a point yet whilst lessen the routing caliber, conventional techniques use brute strength. they typically remodel the matter into mathematical or graph difficulties and fully forget about the categorical wisdom in regards to the routing job which could drastically support the answer. This thesis overcomes many of the above difficulties and provides a approach that plays routing just about what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this region, it doesn't impose pointless constraints, it considers the entire various factors that have an effect on the routing caliber, and most significantly it permits consistent consumer interplay during the routing method. to accomplish the above, this thesis offers history approximately a few consultant strategies for routing and summarizes their features. It then reports intimately different elements (such as minimal quarter, variety of vias, twine size, etc.) that impact the routing caliber, and different standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.
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Am will be performed. The result of these actions might be the creation, deletion, or modification of one or more working memory elements, or some external event such as informing the user of a certain decision. IF C1 C2 ... Cn THEN A1 A2 ... Am Figure 4·3: General form of a rule in a rule-based system. A simple example of a rule in WEAVER is shown in Figure 4-4. The English form of the rule says that if a net is completely routed then remove all the pins belonging to the net from the 48 working memory.
Ml [Ml 84]; and KEE [KEE 84]). Hardware: Hardware effort has concentrated on machines that can execute symbolic manipulation languages, such as LISP and PROLOG, more effiCiently. Examples of these machines include: the Xerox D series machine effort [Xerox 84], the LISP machine from Symbolics [Symbolics 84], the LISP machine from Lisp Machine Incorporated (lMI) [lMI 84], the Explorer from Texas Instrument [TI 84], and the Japanese Prolog Sequential Inference Machine [Murtha 85]. Another effort has been directed in packaging of traditional CPUs, such as the Motorola 68000 [MC68000 82] series, with appropriate hardware and software.
Figure 2·11 (a) shows the initial channel (no net has a pin on the left or right of the channel). Nets 3 and 10 cannot be completed because they are extended to the right side of the channel, but still cannot be connected (each net has two disjoint segments). 14 11616116110161102161102916110293 161102935 [~mImILll[l[ ~~~~~~ 2 25 254 2 5 495 4 143 2549 25495 254954 2549541 2 5 4 9 5 4 1 4 3 1. 5. Hierarchical wire routing Hierarchical wire routing [Burstein 83] has been designed for gate arrays but can be applied to channels and switch-boxes as well.
An Artificial Intelligence Approach to VLSI Routing by R. Joobbani